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RTL Designers, Hyderabad, Bangalore


Company :
Akshaya Consulting Services
Job Location :
Hyderabad, Bangalore
Experience :
3  - 5  yr/s
Contact Person :
Bhaskar
Skills :
Verilog, VHDL
Salary :
3.0 - 5.5 Lacs per annum
No. of Job Positions :
5
Reference Code :
(43470) - Posted on 21-01-2010
Job Description
- Digital design and development (RTL)

- Ability to design and implement moderately defined tasks independently

- Unit level verification to meet various quality guidelines

- Analysis of Spyglass-Lint/ CDC errors/ warnings

- Developing/ running full chip level synthesis flow

- Proactive interaction with RTL designers to resolve warnings/ errors reported during synthesis

- Performing static timing analysis on DC synthesized netlist

Skills/ Experience

- 3 to 5 years of solid experience in digital front end design

- Expertise in Verilog/ VHDL

- Familiarity with various bus protocols like AHB, AXI is highly desired

- Good documentation skills

- Ability to create unit level test plan

- Expertise in Spyglass Lint/ CDC checks and waiver creation

- Understanding of RTL to GDS flow

- Working knowledge of synthesis and STA is a plus

- Expertise in Perl is a plus

- Hands on experience with Design Compiler

- Expert in writing Perl/ TCL scripts

- Ability to experiment with synthesis flows for area reduction and better timing closure

- Ability to understand and analyze RTL written in Verilog/ VHDL

- Good documentation skills
Candidate Profile
RTL, VHDL and STA EXpertise




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