| Company |
Client of Corporate Consultancy Services (CCS) |
| Job Location |
Bangalore |
| Experience |
4 - 8 yr/s |
| Contact Person |
Ramesh Khatawkar
114, BEML Layout, Near Kuvempu Park, 3rd Main, I Stage, Basaveshwar Nagar,
Bangalore
+91-80-2323 2424 |
| Skills |
Analog, SRAM, PLL, DLL, Clock recovery, Oscillators, |
| No. of Job Positions | 1 |
| Reference Code |
DIX-CDE (28441) - Posted on 18-12-2007 |
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| Job Description Job description
Responsible for VLSI Circuit design of high density, high performance DRAM Chips
Circuit design of digital and analog circuits to DRAM architecture, timing and logic design;
The types of circuits will include digital logic for DRAM control and timing voltage reference circuits, change pumps, voltage regulations, densely pitched array circuits, DLLS and IO's
You will mainly work on our full custom VLSI flow to produce best in class DRAM Chips
Domain of experience:
1st preference = Memory design
2nd preference = other custom VLSI circuits (e. g. Clock recovery, DLLs, etc)
Necessary Knowledge/ Tools set:
1. Circuit design fundamentals
2. Understand and participates in Layouts; ideally handles layouts too for his designs
3. In depth Spice based Simulation analyses on back annotated designs
4. Preferred = Coding skills in Perl, SKILL or C
5. Preferred = Exposure to Cadence Composer/ Virtuoso/ Virtuoso XL/ StarRCXT
Should have:
1. We need Circuit design ( Analog) skills
2. Keywords would be Memories, SRAM, PLL, DLL, Clock recovery, Oscillators, A/ D convertors, standard cells layout.
3. Tool usage and exposureCadence Virtuso, Spectre, HSPICE, STAR-RC-XT
Should NOT have:
1. Logic design ( Digital skills)
2. RTL, VHDL, ASIC, SOC, Verilog, Magma, Synthesis
3. VLSI CAD |